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DATA SHEET
MOS INTEGRATED CIRCUIT
PD44321182, 44321362
32M-BIT ZEROSBTM SRAM PIPELINED OPERATION
Description
The PD44321182 is a 2,097,152-word by 18-bit and the PD44321362 is a 1,048,576-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The PD44321182 and PD44321362 are optimized to eliminate dead cycles for read to write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The PD44321182 and PD44321362 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State ("Sleep"). In the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation. The PD44321182 and PD44321362 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for high density and low capacitive loading.
Features
* Low voltage core supply : VDD = 3.3 0.165 V / 2.5 0.125 V * Synchronous operation * 100 percent bus utilization * Internally self-timed write control * Burst read / write : Interleaved burst and linear burst sequence * Fully registered inputs and outputs for pipelined operation * All registers triggered off positive clock edge * 3.3V or 2.5V LVTTL Compatible : All inputs and outputs * Fast clock access time : 3.2 ns (200 MHz) * Asynchronous output enable : /G * Burst sequence selectable : MODE * Sleep mode : ZZ (ZZ = Open or Low : Normal operation) * Separate byte write enable : /BW1 to /BW4 (PD44321362) /BW1 and /BW2 (PD44321182) * Three chip enables for easy depth expansion * Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with NEC Electronics sales representative for availability and additional information.
Document No. M16024EJ5V0DS00 (5th edition) Date Published April 2005 NS CP(K) Printed in Japan
The mark shows major revised points.
2002, 2005
PD44321182, 44321362
Ordering Information
Part number Access Time ns Clock Frequency MHz 200 Core Supply Voltage V 3.3 0.165 2.5 0.125 3.3 V or 2.5 V LVTTL 100-pin PLASTIC LQFP 2.5 V LVTTL 3.3 V or 2.5 V LVTTL 2.5 V LVTTL (14 x 20) I/O Interface Package
PD44321182GF-A50
3.2
PD44321362GF-A50
3.2
200
3.3 0.165 2.5 0.125
2
Data Sheet M16024EJ5V0DS
PD44321182, 44321362
Pin Configurations
/xxx indicates active low signal. 100-pin PLASTIC LQFP (14 x 20) [PD44321182GF]
Marking Side
/BW2 /BW1 /CKE /CE2 ADV CLK CE2 /WE A18 A17 VDD VSS /CE NC NC A6 A7 A8 A9 /G
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC NC VDDQ VSSQ NC NC I/O9 I/O10 VSSQ VDDQ I/O11 I/O12 VDD VDD VDD VSS I/O13 I/O14 VDDQ VSSQ I/O15 I/O16 I/OP2 NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A20 NC NC VDDQ VSSQ NC I/OP1 I/O8 I/O7 VSSQ VDDQ I/O6 I/O5 VSS VDD VDD ZZ I/O4 I/O3 VDDQ VSSQ I/O2 I/O1 NC NC VSSQ VDDQ NC NC NC
MODE
VSS
A5
A4
A3
A2
A1
A0
VDD
NC
A19
A10
A11
A12
A13
A14
A15
Remark Refer to Package Drawings for the 1-pin index mark.
A16
NC
NC
Data Sheet M16024EJ5V0DS
3
PD44321182, 44321362
Pin Identifications [PD44321182GF]
Symbol A0 to A20 Pin No. Description
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input 45, 46, 47, 48, 49, 50, 83, 84, 43, 80
I/O1 to I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In, 18, 19, 22, 23 Synchronous / Asynchronous Data Out Synchronous Data In (Parity), Synchronous / Asynchronous Data Out (Parity)
I/OP1, I/OP2
74, 24
ADV /CE, CE2, /CE2 /WE /BW1, /BW2 /G CLK /CKE MODE
85 98, 97, 92 88 93, 94 86 89 87 31
Synchronous Address Load / Advance Input Synchronous Chip Enable Input Synchronous Write Enable Input Synchronous Byte Write Enable Input Asynchronous Output Enable Input Clock Input Synchronous Clock Enable Input Asynchronous Burst Sequence Select Input Have to tied to VDD or VSS during normal operation
ZZ VDD VSS VDDQ VSSQ NC
64 14, 15, 16, 41, 65, 66, 91 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76
Asynchronous Power Down State Input Power Supply Ground Output Buffer Power Supply Output Buffer Ground
1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 51, No Connection 52, 53, 56, 57, 75, 78, 79, 95, 96
4
Data Sheet M16024EJ5V0DS
PD44321182, 44321362
100-pin PLASTIC LQFP (14 x 20) [PD44321362GF]
Marking Side
/BW4 /BW3 /BW2 /BW1 /CKE /CE2 ADV CLK CE2 /WE A18 A17 VDD VSS /CE A6 A7 A8 A9 /G
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3 I/O17 I/O18 VDDQ VSSQ I/O19 I/O20 I/O21 I/O22 VSSQ VDDQ I/O23 I/O24 VDD VDD VDD VSS I/O25 I/O26 VDDQ VSSQ I/O27 I/O28 I/O29 I/O30 VSSQ VDDQ I/O31 I/O32 I/OP4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/OP2 I/O16 I/O15 VDDQ VSSQ I/O14 I/O13 I/O12 I/O11 VSSQ VDDQ I/O10 I/O9 VSS VDD VDD ZZ I/O8 I/O7 VDDQ VSSQ I/O6 I/O5 I/O4 I/O3 VSSQ VDDQ I/O2 I/O1 I/OP1
MODE
VSS
VDD
NC
A19
A10
A11
A12
A13
A14
A15
Remark Refer to Package Drawings for the 1-pin index mark.
A16
A5
A4
A3
A2
A1
A0
NC
NC
Data Sheet M16024EJ5V0DS
5
PD44321182, 44321362
Pin Identifications [PD44321362GF]
Symbol A0 to A19 Pin No. Description
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input 45, 46, 47, 48, 49, 50, 83, 84, 43
I/O1 to I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29
Synchronous Data In, Synchronous / Asynchronous Data Out
I/OP1 to I/OP4
51, 80, 1, 30
Synchronous Data In (Parity), Synchronous / Asynchronous Data Out (Parity)
ADV /CE, CE2, /CE2 /WE /BW1 to /BW4 /G CLK /CKE MODE
85 98, 97, 92 88 93, 94, 95, 96 86 89 87 31
Synchronous Address Load / Advance Input Synchronous Chip Enable Input Synchronous Write Enable Input Synchronous Byte Write Enable Input Asynchronous Output Enable Input Clock Input Synchronous Clock Enable Input Asynchronous Burst Sequence Select Input Have to tied to VDD or VSS during normal operation
ZZ VDD VSS VDDQ VSSQ NC
64 14, 15, 16, 41, 65, 66, 91 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 38, 39, 42
Asynchronous Power Down State Input Power Supply Ground Output Buffer Power Supply Output Buffer Ground No Connection
6
Data Sheet M16024EJ5V0DS
PD44321182, 44321362
Block Diagrams
[PD44321182]
21 A1 A0 ADV K 19 Burst logic A1' A0' 21
A0 to A20
Address register 0
MODE CLK /CKE Write address register 1 K
21 Write address register 0 21
Output registers
Sense amplifiers
ADV /BW1 /BW2
Memory Cell Array Write registry and data coherency control logic Write drivers 1,024 rows 2,048 x 18 columns (37,748,736 bits)
Output buffers
Data steering
18
18
I/O1 to I/O16 I/OP1, I/OP2
/WE 18
E
E 18
18 Input register 1 E Input register 0 E
/G /CE CE2 /CE2 ZZ
Read logic
Power down control
Burst Sequence [PD44321182] Interleaved Burst Sequence Table (MODE = VDD)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A20 to A2, A1, A0 A20 to A2, A1, /A0 A20 to A2, /A1, A0 A20 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A20 to A2, 0, 0 A20 to A2, 0, 1 A20 to A2, 1, 0 A20 to A2, 1, 1 A20 to A2, 0, 1 A20 to A2, 1, 0 A20 to A2, 1, 1 A20 to A2, 0, 0 A20 to A2, 1, 0 A20 to A2, 1, 1 A20 to A2, 0, 0 A20 to A2, 0, 1 A20 to A2, 1, 1 A20 to A2, 0, 0 A20 to A2, 0, 1 A20 to A2, 1, 0
Data Sheet M16024EJ5V0DS
7
PD44321182, 44321362
[PD44321362]
20 A1 A0 ADV K 18 Burst logic A1' A0' 20
A0 to A19
Address register 0
MODE CLK /CKE Write address register 1 K
20 Write address register 0 20
Output registers
Sense amplifiers
ADV /BW1 /BW2 /BW3 /BW4 /WE
Memory Cell Array Write registry and data coherency control logic Write drivers 1,024 rows 1,024 x 36 columns (37,748,736 bits)
Output buffers
Data steering
36
36
I/O1 to I/O32 I/OP1 to I/OP4
E 36 Input register 1 E
E 36
36 Input register 0 E
/G /CE CE2 /CE2 ZZ
Read logic
Power down control
Burst Sequence [PD44321362] Interleaved Burst Sequence Table (MODE = VDD)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A19 to A2, A1, A0 A19 to A2, A1, /A0 A19 to A2, /A1, A0 A19 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A19 to A2, 0, 0 A19 to A2, 0, 1 A19 to A2, 1, 0 A19 to A2, 1, 1 A19 to A2, 0, 1 A19 to A2, 1, 0 A19 to A2, 1, 1 A19 to A2, 0, 0 A19 to A2, 1, 0 A19 to A2, 1, 1 A19 to A2, 0, 0 A19 to A2, 0, 1 A19 to A2, 1, 1 A19 to A2, 0, 0 A19 to A2, 0, 1 A19 to A2, 1, 0
8
Data Sheet M16024EJ5V0DS
PD44321182, 44321362
State Diagram
DS DS
BURST DS
DESELECT
READ DS DS
WRITE
WRITE READ BEGIN READ READ BEGIN WRITE WRITE
READ
BURST
BURST
WRITE
WRITE BURST BURST READ
READ BURST WRITE BURST
Command DS Read Write Burst Deselect New Read New Write
Operation
Burst Read, Burst Write or Continue Deselect
Remarks 1. States change on the rising edge of the clock. 2. A Stall or Ignore Clock Edge cycle is not shown in the above diagram. This is because /CKE HIGH only blocks the clock (CLK) input and does not change the state of the device.
Data Sheet M16024EJ5V0DS
9
PD44321182, 44321362
Asynchronous Truth Table
Operation Read Cycle Read Cycle Write Cycle Deselected /G L H x x I/O Data-Out High-Z High-Z, Data-In High-Z
Remark x : don't care Synchronous Truth Table
Operation Deselected Deselected Deselected Continue Deselected Read Cycle / Begin Burst Read Cycle / Continue Burst Write Cycle / Begin Burst Write Cycle / Continue Burst Write Cycle / Write Abort Write Cycle / Write Abort Stall / Ignore Clock Edge /CE H x x x L x L x L x x CE2 x L x x H x H x H x x /CE2 x x H x L x L x L x x ADV L L L H L H L H L H x /WE x x x x H x L x L x x /BWs x x x x x x L L H H x /CKE L L L L L L L L L L H CLK LH LH LH LH LH LH LH LH LH LH LH I/O High-Z High-Z High-Z High-Z Data-Out Data-Out Data-In Data-In High-Z High-Z - Address None None None None External Next External Next External Next Current 2 Note 1 1 1 1
Notes
1. Deselect status is held until new "Begin Burst" entry. 2. If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (Lowimpedance). If it occurs during a write cycle, the bus will remain High impedance. No write operation will be performed during the Ignore Clock Edge cycle.
Remarks 1. x : don't care 2. /BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW. /BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH.
10
Data Sheet M16024EJ5V0DS
PD44321182, 44321362
Partial Truth Table for Write Enables [PD44321182]
Operation Read Cycle Write Cycle / Byte 1 (I/O [1:8], I/OP1) Write Cycle / Byte 2 (I/O [9:16], I/OP2) Write Cycle / All Bytes Write Abort / NOP /WE H L L L L /BW1 x L H L H /BW2 x H L L H
Remark x : don't care [PD44321362]
Operation Read Cycle Write Cycle / Byte 1 (I/O [1:8], I/OP1) Write Cycle / Byte 2 (I/O [9:16], I/OP2) Write Cycle / Byte 3 (I/O [17:24], I/OP3) Write Cycle / Byte 4 (I/O [25:32], I/OP4) Write Cycle / All Bytes Write Abort / NOP /WE H L L L L L L /BW1 x L H H H L H /BW2 x H L H H L H /BW3 x H H L H L H /BW4 x H H H L L H
Remark x : don't care ZZ (Sleep) Truth Table
ZZ 0.2 V Open VDD - 0.2 V Chip Status Active Active Sleep
Data Sheet M16024EJ5V0DS
11
PD44321182, 44321362
Electrical Specifications
Absolute Maximum Ratings
Parameter Supply voltage Output supply voltage Input voltage Input / Output voltage Operating ambient temperature Storage temperature Tstg -55 +125 C Symbol VDD VDDQ VIN VI/O TA Conditions MIN. -0.5 -0.5 -0.5 -0.5 0
Note Note
TYP.
MAX. +4.0 VDD VDD + 0.5 VDDQ + 0.5 70
Unit V V V V C
Note -2.0 V (MIN.) (Pulse width : 2 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (VDD = 3.3 0.165 V)
Parameter Supply voltage 2.5 V LVTTL Interface Output supply voltage High level input voltage Low level input voltage 3.3 V LVTTL Interface Output supply voltage High level input voltage Low level input voltage VDDQ VIH VIL 3.135 2.0 -0.3
Note
(1/2)
MIN. 3.135 TYP. 3.3 MAX. 3.465 Unit V
Symbol VDD
Conditions
VDDQ VIH VIL
2.375 2.0 -0.3
Note
2.5
2.9 VDDQ + 0.3 +0.7
V V V
3.3
3.465 VDDQ + 0.3 +0.8
V V V
Note -0.8 V (MIN.) (Pulse width : 2 ns) Recommended DC Operating Conditions (VDD = 2.5 0.125 V)
Parameter Supply voltage Output supply voltage High level input voltage Low level input voltage Symbol VDD VDDQ VIH VIL Conditions MIN. 2.375 2.375 1.7 -0.3
Note
(2/2)
TYP. 2.5 2.5 MAX. 2.625 2.625 VDDQ + 0.3 +0.7 Unit V V V V
Note -0.8 V (MIN.) (Pulse width : 2 ns)
12
Data Sheet M16024EJ5V0DS
PD44321182, 44321362
DC Characteristics (VDD = 3.3 0.165 V or 2.5 0.125 V)
Parameter Input leakage current I/O leakage current Operating supply current Symbol ILI ILO IDD Test condition VIN (except ZZ, MODE) = 0 V to VDD VI/O = 0 V to VDDQ, Outputs are disabled. Device selected, Cycle = MAX. VIN VIL or VIN VIH, II/O = 0 mA Standby supply current ISB Device deselected, Cycle = 0 MHz, VIN VIL or VIN VIH, All inputs are static. ISB1 Device deselected, Cycle = 0 MHz, VIN 0.2 V or VIN VDD - 0.2 V, VI/O 0.2 V, All inputs are static. ISB2 Device deselected, Cycle = MAX. VIN VIL or VIN VIH Power down supply current 2.5 V LVTTL Interface High level output voltage VOH IOH = -2.0 mA IOH = -1.0 mA Low level output voltage VOL IOL = +2.0 mA IOL = +1.0 mA 3.3 V LVTTL Interface High level output voltage Low level output voltage VOH VOL IOH = -4.0 mA IOL = +8.0 mA 2.4 0.4 V V 1.7 2.1 0.7 0.4 V V ISBZZ ZZ VDD - 0.2 V, VI/O VDDQ + 0.2 V 60 mA 130 60 70 mA MIN. -2 -2 TYP. MAX. +2 +2 410 Unit
A A
mA
Capacitance (TA = 25 C, f = 1MHz)
Parameter Input capacitance Input / Output capacitance Clock input capacitance Symbol CIN CI/O Cclk VIN = 0 V VI/O = 0 V Vclk = 0 V Test condition MIN. TYP. MAX. 6.0 8.0 6.0 Unit pF pF pF
Remark These parameters are periodically sampled and not 100% tested.
Data Sheet M16024EJ5V0DS
13
PD44321182, 44321362
AC Characteristics (VDD = 3.3 0.165 V or 2.5 0.125 V)
AC Test Conditions 2.5 V LVTTL Interface Input waveform (Rise / Fall time 2.4 ns)
2.4 V 1.2 V VSS
Test points
1.2 V
Output waveform
1.2 V
Test points
1.2 V
3.3 V LVTTL Interface Input waveform (Rise / Fall time 3.0 ns)
3.0 V 1.5 V VSS
Test points
1.5 V
Output waveform
1.5 V
Test points
1.5 V
Output load condition CL : 30 pF 5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ) Figure External load at test
ZO = 50 I/O (Output) CL
50
VT = +1.2 V / +1.5 V
Remark CL includes capacitances of the probe and jig, and stray capacitances.
14
Data Sheet M16024EJ5V0DS
PD44321182, 44321362
Read and Write Cycle
Parameter Standard Cycle time Clock access time Output enable access time Clock high to output active Clock high to output change Output enable to output active Output disable to output High-Z Clock high to output High-Z Clock high pulse width Clock low pulse width Setup times Address Address advance Clock enable Chip enable Data in Write enable Hold times Address Address advance Clock enable Chip enable Data in Write enable Power down entry time Power down recovery time TKHKH TKHQV TGLQV TKHQX1 TKHQX2 TGLQX TGHQZ TKHQZ TKHKL TKLKH TAVKH TADVVKH TEVKH TCVKH TDVKH TWVKH TKHAX TKHADVX TKHEX TKHCX TKHDX TKHWX TZZE TZZR Symbol Alias TCYC TCD TOE TDC1 TDC2 TOLZ TOHZ TCZ TCH TCL TAS TADVS TCES TCSS TDS TWS TAH TADVH TCEH TCSH TDH TWH TZZE TZZR - - 10 10 ns ns 0.5 (1.0) - (-) ns 3 -A50 (200 MHz) MIN. 5 - - 1.5 1.5 0 0 1.5 1.8 1.8 1.5 MAX. - 3.2 3.2 - - - 3.2 3.2 - - - ns ns ns ns ns ns ns ns ns ns ns 1 1 1, 2 1, 2 Unit Notes
Notes 1. Transition is measured 200 mV from steady state. 2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (TA min., VDD max.) than TKHQZ, which is a max. parameter (worse case at TA max., VDD min.). 3. These values apply when VDD = 3.3 V 0.165 V with a 3.3 V LVTTL interface, or when VDD = 2.5 V 0.125 V with a 2.5 V LVTTL interface. Values in parentheses apply when VDD = 3.3 V 0.165 V with a 2.5 V LVTTL interface.
Data Sheet M16024EJ5V0DS
15
PD44321182, 44321362
READ / WRITE CYCLE
2 TKHKH 3
1
4
5
6
7
8
9
10
CLK
TEVKH TKHEX TKHKL TKLKH
/CKE
TCVKH TKHCX
/CEs
Note 1
TADVVKH TKHADVX
ADV
TWVKH TKHWX
/WE
TWVKH TKHWX
/BWs
Note 2
Address
A1 TAVKH TKHAX High-Z
A2
A3
A4
A5
A6
A7
Data In
D (A1) TDVKH
D (A2)
D (A2+1)
High-Z
D (A5)
High-Z
TKHDX
TKHQX1
TKHQX2 Q (A3) Q (A4)
TGLQV TKHQZ Q (A4+1) TGLQX High-Z TKHQX2 Q (A6)
Data Out
High-Z
TKHQV
TGHQZ
/G
Command
WRITE D (A1)
WRITE D (A2)
BURST WRITE D (A2+1)
READ Q (A3)
READ Q (A4)
BURST READ Q (A4+1)
WRITE D (A5)
READ Q (A6)
WRITE Q (A7)
DESELECT
Notes
1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW. 2. /BWs refers to /BW1, /BW2, /BW3 and /BW4. When /BWs is LOW, any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW.
16
Data Sheet M16024EJ5V0DS
PD44321182, 44321362
NOP, STALL AND DESELECT CYCLE
1
2
3
4
5
6
7
8
9
10
CLK
/CKE
/CEs
ADV
/WE
/BWs
Address
A1
A2
A3
A4
A5
High-Z
Data In
High-Z
D (A1)
High-Z
D (A4)
High-Z TKHQZ
Data Out
Q (A2)
Q (A3)
High-Z
Q (A5) TKHQX2
Command
WRITE D (A1)
READ Q (A2)
STALL
READ Q (A3)
WRITE D (A4)
STALL
NOP
READ Q (A5)
DESELECT
CONTINUE DESELECT
Data Sheet M16024EJ5V0DS
17
PD44321182, 44321362
POWER DOWN (ZZ) CYCLE
1
2
TKHKH
3
4
5
6
7
8
9
10
11
12
CLK
TKHKL TKLKH
/CKE
/CEs Note
ADV
/WE Note
/BWs
Address
A1
A2
/G
Data Out
High-Z Q (A1)
High-Z
Q1 (A2)
ZZ
TZZE Power Down (ISBZZ) State TZZR
Note /WE or /CEs must be held HIGH at CLK rising edge (clock edge No.2 and No.3 in this figure) prior to power down state entry.
18
Data Sheet M16024EJ5V0DS
PD44321182, 44321362
Package Drawing
100-PIN PLASTIC LQFP (14x20)
A B
80 81
51 50
detail of lead end S C D R Q
100 1
31 30
F G H I
M
J
K P S
N
S
L M
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 22.00.2 20.00.2 14.00.2 16.00.2 0.825 0.575 0.32 +0.08 -0.07 0.13 0.65 (T.P.) 1.00.2 0.50.2 0.17 +0.06 -0.05 0.10 1.4 0.1250.075 +7 3 -3 1.7 MAX. S100GF-65-8ET-1
Data Sheet M16024EJ5V0DS
19
PD44321182, 44321362
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the PD44321182 and PD44321362. Types of Surface Mount Devices
PD44321182GF : 100-pin PLASTIC LQFP (14 x 20) PD44321362GF : 100-pin PLASTIC LQFP (14 x 20)
20
Data Sheet M16024EJ5V0DS
PD44321182, 44321362
Revision History
Edition/ Date This edition 5th edition/ Apr. 2005 p.12 p.12 Throughout Page Previous edition Throughout Modification Deletion - - Preliminary Data Sheet Data Sheet -A60, -A50Y, -A60Y VIH (MIN.) : 1.7 V 2.0 V Type of revision Location Description (Previous edition This edition)
Modification Recommended DC Operating Conditions (1/2)
Data Sheet M16024EJ5V0DS
21
PD44321182, 44321362
[MEMO]
22
Data Sheet M16024EJ5V0DS
PD44321182, 44321362
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions.
5
POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.
Data Sheet M16024EJ5V0DS
23
PD44321182, 44321362
ZEROSB is a trademark of NEC Electronics Corporation.
* The information in this document is current as of April, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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